The present invention relates to semiconductor memory devices and, more particularly, to source/drain regions of semiconductor memory devices and methods of manufacturing the same.
As the density of integrated circuit (semiconductor) memory devices continues to increase, and the corresponding design rule of the devices becomes finer, a width of a gate pattern in the semiconductor memory devices has been gradually reduced. An effective channel length of the gate pattern has also been shortened as the width of the gate pattern decreases. As a result, a short channel effect, resulting in a punch-through effect between a source region and a drain region, may be more frequently generated.
Source/drain regions having a lightly doped drain (LDD) structure capable of allowing a shallow junction may be used to address the punch-through effect. However, when the width of the gate pattern is no greater than about 0.35 μm, the source/drain regions having the LDD structure may not sufficiently suppress the short channel effect because of limitations on forming of the shallow junction in the source/drain regions having the LDD structure. Elevated source/drain regions formed by a selective epitaxial growth (SEG) process may, therefore, be used in semiconductor memory devices having a gate pattern, which has, for example, a width of no more than about 0.35 μm, to suppress the short channel effect.
An example of a semiconductor memory device having elevated source/drain regions using an SEG process is described in Korean Patent Laid-Open Publication No. 2004-98302. FIG. 1 is a cross-sectional view illustrating a semiconductor memory device having elevated source/drain regions that are formed by a conventional method.
Referring to FIG. 1, a gate pattern 12 is shown formed on a semiconductor (integrated circuit) substrate 10. A gate spacer 14 is shown formed on a sidewall of the gate pattern 12. The illustrated gate pattern 12 includes a gate insulation layer, a gate conductive layer and a hard mask layer that are sequentially stacked. The gate spacer 14 may be silicon nitride.
As also illustrated in FIG. 1, source/drain regions 16a and 16b are formed on the semiconductor substrate 10. The source/drain regions 16a and 16b make contact with the gate spacer 14. In other words, the source/drain regions 16a and 16b have an elevated structure relative to an upper surface of the semiconductor substrate 10.
The elevated source/drain regions 16a and 16b may be formed by an SEG process. The above-mentioned Korean Patent describes a method of forming the elevated source/drain regions by performing an SEG process twice. Specifically, after a first SEG process is carried out at a low temperature, a second SEG process is performed at a high temperature.
However, when the elevated source/drain regions 16a and 16b are formed by the SEG process, a large number of facets may be generated at upper edge portions of the elevated source/drain regions 16a and 16b where they contact with the gate spacer 14. When the second SEG process is carried out at a high temperature, the facets may be generated more frequently at the upper edge portions of the elevated source/drain regions. That is, although the elevated source/drain regions may have some improved properties when generated by the second SEG process at a high temperature, as compared with the first SEG process at a low temperature, the problematic facets may be more frequently generated by the second SEG process.
When the elevated source/drain regions 16a and 16b are doped with impurities, the impurities may be implanted into relatively deep positions in the elevated source/drain regions 16a and 16b through the facets so that the short channel effect may be still generated.